1. Field of the Invention
Example embodiments of the present invention relate to semiconductor memory devices having one or more signal delay controllers and methods performed therein.
2. Description of the Conventional Art
As semiconductor memory devices become increasingly integrated they may be decreased in size. As semiconductor memory devices become smaller, the number of net dies per wafer may be reduced.
Semiconductor memory devices may be divided into a plurality of cell array blocks, and may include a row decoder and a column decoder. The row decoder may designate a word line to connect to a unit memory cell, and the column decoder may designate a bit line to connect to a unit memory cell.
FIG. 1 is a block diagram schematically illustrating a conventional semiconductor memory device. As shown, the conventional semiconductor memory device of FIG. 1 may include a memory cell array 10, a peripheral circuit region 16, row decoders 12 and column decoders 14.
The memory cell array 10 may have a plurality of unit memory cells connected to each intersection of bit lines and word lines. When an address is input through an address pin, the bit line and word line may be selected by the row decoder 12 and the column decoder 14, respectively, for decoding the address. The peripheral circuit region 16 may include circuits needed for operation.
In the semiconductor memory device of FIG. 1, path distances between the row decoder 12 and word lines or the column decoder 14 and bit lines within the memory cell array 10 may be similar or substantially similar. In other words, the differences in path distances may be similar or substantially similar. In the memory cell array 10, delay of a signal output from the row decoder 12 to a word line, from a column decoder 14 and to a bit line within the memory cell array 10 and signal skew caused by a voltage variation may not be a problem.
However, as capacity of semiconductor memory devices increases, delay of a signal output from a row decoder to a word line or from column decoder to a bit line within a memory cell array may increase and/or cause a voltage variation resulting in a signal skew.
FIG. 2 is a block diagram illustrating an output path of data in a conventional semiconductor memory device. FIG. 2 shows a row address buffer 20, a row decoder 22, a memory core 26, a data output buffer 28, a column address buffer 21 and a column decoder 23.
The row address buffer 20 may change an external address EXT_ADDX to an internal address INT_ADDX. The row address buffer 20 may operate in response to a row address strobe/RAS.
The row decoder 22 may receive the internal address INT_ADDX and may select a word line connected to an access memory cell. The row decoder 22 may be divided into and/or include a predecoder and a main decoder. However, for the sake of brevity a detailed discussion has been omitted.
The column address buffer 21 may receive an external address EXT_ADDY and may output an internal address INT_ADDY. The column decoder 23 may receive the internal address INT_ADDY and may output data of a bit line. The data may be amplified by a sense amplifier within the memory core 26, and may be output through a data output buffer 28. The memory core 26 may include a plurality of unit memory cells arranged in an array (referred to hereinafter as a cell array or memory cell array), a word line and bit line connected to the unit memory cell and a sense amplifier connected to the bit line.
FIG. 3 is a block diagram schematically illustrating a structure of another conventional semiconductor memory device. As shown, the conventional semiconductor memory device of FIG. 3 may include a memory cell array 30, a peripheral circuit region 36, a row decoder 32 and a column decoder 34. The cell array 30 may be divided into regions or blocks A, B, C and D.
In operation, access times for row decoder 32 to access memory cells in regions A and D may be longer than access times for row decoder 32 to access memory cells of regions B and C. For example, row address access time (tRAC) for memory cells in regions A and D may be longer than tRAC of memory cells in regions B and C. The tRAC represents a time interval from input of an effective row address (e.g., a transition time point of/RAS) to output of effective data (e.g., in response to a row address strobe/RAS).
Similarly, column address access time (tCAC) for column decoder 34 to access memory cells in regions A and B may be longer than column address access time tCAC for column decoder 34 to access memory cells in regions C and D. The tCAC represents a time interval from input of an effective column address point (e.g., a transition time point of/CAS) to output of effective data (e.g., in response to a column address strobe/CAS). The column address strobe/CAS may transition after the row address strobe/RAS.
When a decoding signal, decoded by the row decoder 32 or column decoder 34, is input to the memory cell array 30, path lengths for accessing unit memory cells within the memory cell array 30 may differ for one or more of the regions A, B, C and D. For example, access to a cell further from the row decoder 32 or column decoder 34 may have a larger line loading capacitance relative to a closer cell. Additionally, in accessing cells further from the row decoder 32 or column decoder 34 signal skew generation due to a voltage level change of decoding signal output from the row decoder 32 or column decoder 34 may be more likely.
For example, for the row decoder 32, a boosted voltage level VPP of memory cells in regions A and D within the memory cell array 30 may be changed and there may be an increased possibility of signal skew generation, as compared with memory cells in regions B and C. For column decoder 34, in memory cells in regions A and B within the memory cell array 30, a level of voltage output by an internal voltage converter (IVC) may vary. This may increase a signal skew generation rate.
In one example, to reduce delay and/or the likelihood of signal skew, a memory cell array may be divided into smaller units or a line through which a signal for accessing the memory cell array may be used. However, the above may result in increased chip size due to additional row decoders, column decoders and/or only a single line corresponding to a determined portion of the memory cell array.
In another example, to reduce delay and/or the likelihood of signal skew, a line including a delay device in a memory cell array adjacent to a row decoder or column decoder may be added. The line may be formed of material having a higher resistance or a path of a signal may be lengthened. However, conventional semiconductor memory devices employing these above examples may have a structure in which a line is wired on a region not adjacent to a row decoder or column decoder. This may increase bus problems, restrict process and/or chip size due to a lengthened wiring line.
In conventional semiconductor memory devices, as described above, access times from a row decoder or column decoder may differ based on which portion of the memory cell array is to be accessed. These different access times may cause signal delay when accessing the memory cell array and/or skew of signal accessing the memory cell array may occur. Different access times and/or signal skew may cause operational errors.